Verification and Validation Based on System Engineering Process Theory
Received:July 11, 2017  Revised:November 15, 2017
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DOI:10.7643/ issn.1672-9242.2017.11.005
KeyWord:system engineering  verification  validation
     
AuthorInstitution
DENG Lin The 29th Research Institute of China Electronics Technology Group Corporation, Chengdu , China
DENG Ming The 29th Research Institute of China Electronics Technology Group Corporation, Chengdu , China
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Abstract:
      To analyze the relationship between verification and validation of engineering processes and clarify the roles and methods of both, this paper analyzed and discussed the two concepts from traceability, similarities and differences, relationship analysis, method application, etc. Verification and validation are two important technical processes in system engineering. Methods of several activities in two processes are similar, even the same, and confusing. The results show that their purposes were different, while their methods were similar. Verification and validation are two very important sub-processes in technical process of system engineering. They are essential for the integral process. Their difference is that: the verification process is to determine the design process and the results are correct, the confirmation process is to determine the design of the object is correct. They are in line with the needs of stakeholders.
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