Optimization of Multi-chip Layout and Heat Sink Structure Parameters Based on Grey Relational Analysis
Received:September 17, 2020  Revised:January 04, 2021
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DOI:10.7643/issn.1672-9242.2021.06.021
KeyWord:multi-chip layout  heat sink  thermal simulation  grey relational analysis
        
AuthorInstitution
ZHANG Rong-feng Casco Signal Ltd, Shanghai , China
WANG Yong Casco Signal Ltd, Shanghai , China
LIU Tao Casco Signal Ltd, Shanghai , China
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Abstract:
      Aiming at reducing the temperature rise of the chip and improve the thermal reliability of the chip, CFD simulation tools were used to build a thermal simulation analysis model of a multi-chip shared heat sink to determine the junction temperature rise of the chips. The relationship between the seven structural parameters (the chips horizontal and vertical spacing, the thickness of the heat sink baseplate, the fin height, the fin thickness, and the horizontal fin spacing and the number of longitudinal fins) and the chips maximal temperature rise were analyzed. The main influencing factors were screened out through grey relational analysis and optimized by response surface analysis.The grey correlation degree of the four factors was greater than 0.6, which are the main factors that affected the temperature rise of the chips. The influence order was:the number of vertical fins>the thickness of the substrate>the horizontal spacing of chips>the thickness of the fin; the horizontal fin spacing. Fin height, and vertical chip spacing were secondary factors. The final combination optimization parameters were further obtained through response surface analysis optimization:the chip longitudinal spacing is 15 mm, the fin height is 18mm, and the fin spacing is 6 mm; the chip lateral spacing is 104 mm, the substrate thickness is 11.2 mm, the fin thickness is 1.13 mm, the number of longitudinal fins is 10, and the maximum simulated temperature rise of the chipset is 48.959 ℃. Grey relational analysis can be better used to analyze the influence of multiple factors on heat dissipation, and build a high-precision regression prediction model when combining with response surface analysis. This research can provide reference for the evaluation and optimization of the chips layout and structure of the multi-chip shared heat sink.
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